View SST30VR043-500-C-EH_1025769.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ? 2000 silicon storage technology, inc. the sst logo and superflash are registered trademarks of silicon storage technology, inc . combomemory is a trademark of 378-03 2/00 silicon storage technology, inc. these specifications are subject to change without notice. features: ? organized as 512k x8 rom + 32k x8 sram ? rom/ram combo on a monolithic chip ? wide operating voltage range: 2.7-3.3v ? chip access time C 2.7v operation: 500 ns (max.) ? low power dissipation: C standby 3.0v operation: 1.0w (typical) C operating 3.0v operation: 3.0 mw (typical) product description the sst30vr043 is a rom/ram combo chip consist- ing of 4 mbit read only memory organized as 512 kbytes and a 256 kbit static random access memory organized as 32 kbytes. output enable input (oe#) is pin-shared with ramcs# (ram enable input) signal in order to maintain the standard 32 pin tsop package. the device is fabricated using ssts advanced cmos low power process technology. ? fully static operation C no clock or refresh required ? three state outputs ? packages available C 32-pin tsop (8mm x 20mm) C 32-pin stsop (8mm x13.4mm) the sst30vr043 has an output enable input for precise control of the data outputs. it also has two (2) separate chip enable inputs for selection of either ram or rom and minimize current drain during power-down mode. the sst30vr043 is particularly well suited for use in low voltage (2.7-3.3v) operation such as pagers, organizers and other handheld applications. f unctional b lock d iagram of sst30vr043 rom/ram c ombo ramcs# oe#/ramcs# romcs# we# a 15 -a 18 dq 0 -dq 7 a 0 -a 14 romcs# 256k ram 4m rom web oeb oeb 378 ill b1.2 control circuit address buffer data buffer
2 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet absolute maximum stress ratings (applied conditions greater than those listed under absolute maximum stress ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) voltage on any pin relative to v ss ............................................................................................................................. -0.5v to v dd + 0.5v voltage on v dd supply relative to v ss ............................................................................................................................... ...... -0.5 to 4.0v power dissipation .............................................................................................................. ................................ 1.0w storage temperature ............................................................................................................ .......... -65c to +150c operating temperature .......................................................................................................... ........... -20c to +70c soldering temperature (10 seconds lead only) ................................................................................... .......... 260c f igure 1: p in a ssignments t able 1: p in d escription symbol pin name a 0 -a 18 address inputs we# write enable input oe#/ramcs# output enable/ram enable input romcs# rom enable input dq 0 -dq 7 data inputs/outputs v dd power supply vss ground 378 pgm t1.1 ac c onditions of t est input pulse level ........................ 0-3v input & output timing reference levels .................. 1.5v input rise/fall time .................... 5 ns output load ................................ c l = 100 pf o perating r ange range ambient temp v dd commercial 0 c to +70 c 2.7-3.3v extended -20 c to +70 c 2.7-3.3v industrial -40 c to +85 c 2.7-3.3v a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe#/ramcs# a10 romcs# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 378 ill f01.2 standard pinout top view die up
3 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t able 2: r ecommended dc o perating c onditions symbol parameter min max units v dd supply voltage 2.7 3.3 v v ss ground 0 0 v v ih input high voltage 2.4 v dd +0.5 v v il input low voltage -0.3 0.3 v 378 pgm t2.0 t able 3: dc o perating c haracteristics v dd = 3.00.3v symbol parameter min max units test conditions i li input leakage current -1 1 a v in =v ss to v dd i lo output leakage current -1 1 a romcs# = ramcs# = v ih or oe# = v ih or we# = v il , v i/o = v ss to v dd i dd1 rom operating 4.0+1.1(f) ma romcs# = v il , ramcs# = v ih , v in = v ih or v il supply current i i/o = opens i dd2 ram operating 2.5+1(f) ma romcs# = v ih , ramcs# = v il , i i/o = opens supply current i sb standby v dd current 10 a romcs# 3 v dd -0.2v, ramcs# 3 v dd -0.2v v in 3 v dd -0.2v or v in 0.2v v ol output low voltage 0.4 v i ol = 1.0 ma v oh output high voltage 2.2 v i oh = -0.5 ma note: f = 1/cycle time (mhz) 378 pgm t3.2 t able 4: c apacitance (ta = 25 c, f=1 mhz) parameter description test condition maximum c i/o i/o capacitance v i/o = 0v 8 pf c in input capacitance v in = 0v 6 pf 378 pgm t4.0 f igure 2: ac i nput /o utput r eference w aveforms ac test inputs are driven at v iht (0.9 v dd ) for a logic 1 and v ilt (0.1 v dd ) for a logic 0. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). inputs rise and fall times (10% ? 90%) are <5 ns. note: v ht Cv high test v lt Cv low test v iht Cv input high test v ilt Cv input low test 378 ill f07.0 reference points output input v it v iht v ilt v ot
4 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet ac characteristics i. rom operation f igure 4: rom r ead c ycle t iming d iagram (a ddress c ontrolled ) (romcs# = oe# = v il ) t rc t aa data valid 378 ill f02.0 data out previous data valid address t oh t able 5: r ead c ycle t iming p arameters v dd =3.0 v 0.3 symbol parameter min max unit t rc read cycle time 500 ns t aa address access time 500 ns t co chip select to output 500 ns t oe output enable to valid output 250 ns t lz chip select to low-z output 10 ns t olz output enable to low-z output 10 ns t hz chip disable to high-z output 40 ns t ohz output disable to high-z output 40 ns t oh output hold from address change 15 ns 378 pgm t5.2 378 ill f08.0 to tester to dut c l f igure 3: a t est l oad e xample
5 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 5: rom r ead c ycle t iming d iagram (romcs# & oe# c ontrolled ) ii. sram operation (romcs# = v ih ) 378 pgm t6.2 t able 6: r ead c ycle t iming p arameters v dd =3.0 v 0.3 symbol parameter min max unit t rc read cycle time 500 ns t aa address access time 500 ns t co chip select to output 500 ns t lz chip select to low-z output 10 ns t hz chip disable to high-z output 40 ns t oh output hold from address change 15 ns t able 7: w rite c ycle t iming p arameters v dd =3.0 v 0.3 symbol parameter min max unit t wc write cycle time 500 ns t cw chip select to end-of-write 365 ns t aw address valid to end-of-write 400 ns t as address set-up time 0 ns t wp write pulse width 400 ns t wr write recovery time 0 ns t whz write to output high-z 80 ns t dw data to write time overlap 200 ns t dh data hold from write time 0 ns t ow end write to output low-z 10 ns 378 pgm t7.1 t rc t aa t co t lz(2) t ohz(1) t oh t hz(1,2) data valid 378 ill f03.1 data out oe# romcs# high-z address t oe t olz notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are referenced to the v oh or v ol . 2. at any given temperature and voltage condition t hz (max) is less than t lz (min) both for a given device and from device to device.
6 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet f igure 6: sram r ead c ycle t iming d iagram (a ddress c ontrolled ) (oe#/ramcs# = v il , we# = v ih ) f igure 7: sram r ead c ycle t iming d iagram (oe#/ramcs# c ontrolled ) t rc t aa data valid 378 ill f04.0 data out previous data valid address t oh t rc t aa t co t lz(2) t oh t hz(1,2) data valid 378 ill f05.2 data out oe#/ramcs# high-z address notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are referenced to the v oh or v ol . 2. at any given temperature and voltage condition t hz (max) is less than t lz (min) both for a given device and from device to device. 3. we# is high for read cycle.
7 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 8: sram w rite c ycle t iming d iagram t wc t aw t cw(2) t oh t dh t dw t ow t wr(4) data valid 378 ill f06.2 data in data out we# oe#/ramcs# high-z high-z (6) (7) (8) address t wp(1) t as(3) t whz(5) notes: 1. a write occurs during the overlap (t wp ) of a low ramcs# and low we#. a write begins at the latest transition among ramcs# going low and we# going low: a write end at the earliest transition among ramcs# going high and we# going high, t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of ramcs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. 5. if ramcs#, we# are in the read mode during this period, the i/o pins are in the outputs low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 6. if ramcs# goes low simultaneously with we# going low or after we# going low, the outputs remain high impedance state. 7. d out is the same phase of the latest written data in this write cycle. 8. d out is the read data of new address 9. romcs# = v ih
8 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet t able 8: f unctional d escription /t ruth t able a0=a18 romcs# oe#/ramcs# we# dq 0 -dq 7 (pin 32) x h h x z standby a0-a18 l oe# (h) x z output floating a0-a18 l oe# (l) x dout rom read only a0-a14 are valid * h ramcs# (l) h dout ram read only a0-a14 are valid * h ramcs# (l) l din ram write * a15-a18 must be fixed to l or h note: (1) oe# & ramcs# are pin-shared ( 2) x means dont care. 378 pgm t9.1
9 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 device speed suffix1 suffix2 sst30vr043 - xxx - x - xx - rxxxx c-spec number package modifier h = 32 leads numeric = die modifier package type k = tsop (die up) 8mm x 13.4mm e = tsop (die up) 8mm x 20mm u = die only temperature range c = commercial = 0 to 70c e = extended = -20 to 70c i = industrial = -40 to 85c read access speed 500 = 500 ns density 043 = 4 mbit rom + 256 kbit sram voltage range v = 2.7-3.3v device family 30 = rom/ram combo sst30vr043 valid combinations sst30vr043-500-c-kh SST30VR043-500-C-EH sst30vr043-500-c-u1 sst30vr043-500-e-kh sst30vr043-500-e-eh sst30vr043-500-i-kh sst30vr043-500-i-eh example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
10 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 32-p in t hin s mall o utline p ackage (tsop) 8 mm x 13.4 mm sst p ackage c ode : kh packaging diagrams 32.tsop-kh-ill.4 note: 1. complies with jedec publication 95 mo-142 ba dimensions (except as noted), although some dimensions may be more string ent. ? = jedec max is 8.1; sst max is less stringent 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 7.90 8.30 ? .16 .27 .91 1.05 .50 bsc 0.05 0.20 11.70 11.90 pin # 1 alternate indicator 13.20 13.60 0.70 0.30
11 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-p in t hin s mall o utline p ackage (tsop) 8 mm x 20 mm sst p ackage c ode : eh 32.tsop-eh-ill.3 note: 1. complies with jedec publication 95 mo-142 bd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 8.10 7.90 .27 .17 1.05 0.95 .50 bsc 0.15 0.05 18.50 18.30 20.20 19.80 0.70 0.50 pin # 1 identifier
12 ? 2000 silicon storage technology, inc. 378-03 2/00 4 megabit rom + 256 kilobit sram rom/ram combo sst30vr043 data sheet silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.ssti.com ? literature faxback 888-221-1178, international 732-544-2873

▲Up To Search▲

Price & Availability of SST30VR043-500-C-EH

	To Download SST30VR043-500-C-EH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .